VLSI Projects - B-Tech Projects -
S No IEEE Project Title Price Base Papers Screen Shorts Buy Project
1 2017 A Novel Area-Efficient VLSI ArchitectureFor Recursion Computation In LTETurbo Decoders coming soon
2 2017 Design A DSP Operations Using Vedic Mathematics coming soon
3 2017 A Novel Approach For Parallel CRC Generation For High Speed Application coming soon
4 2017 An Efficient Implementation Of Floating Point Multiplier coming soon
5 2017 Design And Implementation Of Carry Select Adder Without Using Multiplexers coming soon
6 2017 32-bit decimalmatrix with sram coming soon
7 2017 A High Speed Binary Floating Point Multiplier Using Dadda Algorithm coming soon
8 2017 Design of High Speed Low Power Multiplier Using Reversible Logic A Vedic Mathematical Approach coming soon
9 2017 Trade-Offs for Threshold ImplementationsIllustrated on AES coming soon
10 2017 Efficient Coding Schemes for Fault-TolerantParallel Filters coming soon
11 2017 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication coming soon
12 2017 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks coming soon
13 2017 Implementation of High Speed Low Power Combinational and Sequential Circuits using Reversible logic coming soon
14 2017 A Decimal Binary Multi-operand Adder using a Fast Binary to Decimal Converter coming soon
15 2017 Low-Power and Area-Efficient Shift Register Using Pulsed Latches coming soon
16 2017 Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” coming soon
17 2017 Fully Reused VLSI Architecture ofFM0Manchester Encoding Using SOLS coming soon
18 2017 A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications coming soon
19 2017 3 input xor or xnor gate coming soon
20 2017 Design Of high Performance 64 Bit MAC Unit coming soon
21 2017 Multi operand Redundant Adders on FPGAs . coming soon
22 2017 high speed convolution and deconvolution algorithm coming soon
23 2017 Design and Analysis of Approximate Compressors for Multiplication coming soon
24 2017 Low-Power Programmable PRPG With Test Compression Capabilities coming soon
25 2017 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay coming soon
26 2017 Area-Delay Efficient Binary Adders in QCA coming soon
27 2017 Split SAR ADCs Improved Linearity With Power and Speed Optimization coming soon
28 2017 A novel approach to realize Built-in-self-test(BIST) enabled UART using VHDL coming soon
29 2017 A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving coming soon